15 %org 0. 16 000 3FFFFFFE 18 End_of_phase: end. 19 End_of_link: chan neg_lsl; 001 7FFFFEFE 20 end. 21 23 %include 'pwm.uc' ;function = $F. 1 (**********************************************************************) 2 (* *) 3 (* Function: PWM - Pulse Width Modulation *) 4 (* *) 5 (* Creation Date: Pre 89 From: NEW *) 6 (* *) 7 (* Author: Motorola *) 8 (* *) 9 (* Description: *) 10 (* ------------ *) 11 (* Generate pulse width modulated waveform, CPU supplies period & H.T *) 12 (* 0% and 100% specially handled to be independant of latency issues. *) 13 (* *) 14 (* IMPORTANT NOTES : *) 15 (* 1. PWMHI and PWMPER must be read coherently, note that no *) 16 (* ram access is done in the cycle before they are read. !!! *) 17 (* *) 18 (* Updates: By: Modification: *) 19 (* -------- --- ------------- *) 20 (* 28/Feb/92 JW Cleaned up for inclusion in Library *) 21 (* 11/Apr/93 JL Convert to new syntax & changed unused link *) 22 (* states to End_of_Link. *) 23 (* *) 24 (*--------------------------------------------------------------------*) 25 (* Standard Exits Used:- End_Of_Phase: Y End_Of_Link: N *) 26 (* *) 27 (* External Files %included: NONE. *) 28 (* *) 29 (* CODE SIZE excluding standard exits = 32 LONG WORDS *) 30 (*--------------------------------------------------------------------*) 31 (* *) 32 (* *) 33 (********** This Revision: 2.0 *********) 34 (* *) 35 (* Functionally identical to 68332 TPU ROM of masks D33F, D87M, 2D87M *) 36 (* *) 37 (********** LAST MODIFIED: 11/Apr/93 BY: Jeff Loeliger ********) 38 (* *) 39 (**********************************************************************) 40 (***************************************************************************) 41 (*Motorola reserves the right to make changes without further notice to any*) 42 (*product herein. Motorola makes no warranty, representation or guarantee *) 43 (*regarding the suitability of its products for any particular purpose, nor*) 44 (*does Motorola assume any liability arising out of the application or use *) 45 (*of any product or circuit, and specifically disclaims any and all *) 46 (*liability, including without limitation consequential or incidental *) 47 (*damages. "Typical" parameters can and do vary in different applications. *) 48 (*All operating parameters, including "Typical",must be validated for each *) 49 (*customer application by customer's technical experts. Motorola does not *) 50 (*convey any license under its patent rights nor the rights of others. *) 51 (*Motorola products are not designed, intended, or authorized for use as *) 52 (*components in systems intended for surgical implant into the body, or *) 53 (*other applications intended to support or sustain life, or for any other *) 54 (*application in which the failure of the Motorola product could create a *) 55 (*situation where injury or death may occur. Should Buyer purchase or use *) 56 (*Motorola products for any such unintended or unauthorized application, *) 57 (*Buyer, shall indemnify and hold Motorola and its officers, employees, *) 58 (*subsidiaries, affiliates, and distributors harmless against all claims, *) 59 (*costs, damages, and expenses, and reasonable attorney fees arising out *) 60 (*of, directly or indirectly, any claim of personal injury or death *) 61 (*associated with such unintended or unauthorized use, even if such claim *) 62 (*alleges that Motorola was negligent regarding the design or manufacture *) 63 (*of the part. *) 64 (*Motorola and the Motorola logo are registered trademarks of Motorola Inc.*) 65 (*Motorola is an Equal Opportunity/Affirmative Action Employer. *) 66 (*Copyright Motorola Inc. 1993 *) 67 (***************************************************************************) 68 69 (* Parameters *) 70 71 %macro CHANNEL_CONTROL_PWM 'prm0'. 72 %macro OLDRIS 'prm1'. 73 %macro PWMHI 'prm2'. 74 %macro PWMPER 'prm3'. 75 %macro PWMRIS 'prm4'. 76 77 %macro CHAN_CONT_REG 'p_low'. 78 79 (**********************************************************************) 80 (* *) 81 (* STATE : Init_pwm *) 82 (* *) 83 (* PRELOAD PARAMETER : CHANNEL CONTROL *) 84 (* *) 85 (* ENTER WHEN : HSR10 is issued *) 86 (* *) 87 (* ACTION : *) 88 (* 1.OLDRIS gets the value of the matched tcr *) 89 (* 2.pin is asserted *) 90 (* 3.Init_cycle is called *) 91 (* 4.Match is generated on OLDRIS + PWMHI *) 92 (* 5.Interrupt request is asserted *) 93 (* *) 94 (**********************************************************************) 95 %entry start_address *; ram p<-@CHANNEL_CONTROL_PWM; disable_match; 96 name = Init_pwm; 97 cond hsr1=1,hsr0=0. 98 99 100 Init_pwm : 101 au nil :=<< @CHAN_CONT_REG, ccl; 002 E1E401C7 102 chan clear flag0. 103 104 chan config := p, enable_mtsr; 003 8E06FEF8 105 if N = 0 then goto Normal_L_H. 106 107 Get_tcr1 : 108 au ert := tcr1; 004 7859FEFF 109 chan neg_tdl, neg_mrl, neg_lsl. 110 111 Get_tcr2 : 112 au ert := tcr2; 005 7A59FEFF 113 chan neg_tdl, neg_mrl, neg_lsl. 114 115 116 (**********************************************************************) 117 (* *) 118 (* STATE : Normal_L_H , Normal_100 *) 119 (* *) 120 (* PRELOAD PARAMETER : OLDRIS *) 121 (* *) 122 (* ENTER WHEN : low to high transition occured *) 123 (* (also when executing 100% duty cycle) *) 124 (* *) 125 (* ACTION : *) 126 (* 1.current time is stored is OLDRIS *) 127 (* 2.Init_cycle is called *) 128 (* 3.high_low match is generated on OLDRIS+PWMHI *) 129 (* 4.Interrupt request is asserted *) 130 (* *) 131 (**********************************************************************) 132 %entry start_address *; ram p<-@OLDRIS; 133 name = normal_l_h; 134 cond hsr1=0,hsr0=0,m/tsr=1,lsr=0,pin=1,flag0=x. 135 136 Normal_L_H : 137 au diob := ert; 006 3C7FF807 138 ram diob -> @OLDRIS. 139 140 call_init_cycle : 007 D409FFFF 141 call Init_cycle, flush. 142 (* on return a = PWMHI, sr = OLDRIS diob = PWMPER *) 143 144 au ert := a + sr; 145 chan write_mer, neg_mrl,pac := high_low; 146 chan cir; 008 525CB5FA 147 end. 148 149 150 (**********************************************************************) 151 (* *) 152 (* PROCEDURE : Init_cycle *) 153 (* *) 154 (* CALLED BY : *) 155 (* *) 156 (* ACTION : *) 157 (* 1.PWMHI and PWMPER are read coherently *) 158 (* 2.PWMRIS := OLDRIS + PWMPER *) 159 (* #3.If PWMHI = 0 then *) 160 (* flag0 is chan set *) 161 (* no_change match is generated on OLDRIS+ PWMPER *) 162 (* interrupt request is asserted *) 163 (* pin is cleared *) 164 (* *) 165 (* 3.If PWMHI >= PWMPER then *) 166 (* flag0 is chan set *) 167 (* no_change match is generated on OLDRIS+ PWMPER *) 168 (* interrupt request is asserted *) 169 (* pin is chan set *) 170 (* *) 171 (* *) 172 (* PARAMETERS & REGISTERS : *) 173 (* *) 174 (* ON ENTRY *) 175 (* diob - OLDRIS *) 176 (* a - UNKNOWN *) 177 (* sr - UNKNOWN *) 178 (* ON EXIT *) 179 (* diob - PWMPER *) 180 (* a - PWMHI *) 181 (* sr - OLDRIS *) 182 (* *) 183 (* NOTE : The coherency of PWMPER and PWMHI reading is guaranteed *) 184 (* by the call to Init_cycle wich is always done with a *) 185 (* FLUSH!!!! *) 186 (* *) 187 (**********************************************************************) 188 Init_cycle : 189 190 au sr := diob; 009 163FF00B 191 ram p <- @PWMHI. 192 193 au a := p, ccl; 00A 101DF80F 194 ram diob <- @PWMPER. 195 196 Check_duty_cycle : 00B 8610FFFF 197 if LOW_SAME = 1 then goto duty_0. 198 199 au p := diob + sr; 00C 36FEB013 200 ram p -> @PWMRIS. 201 00D 37FC4FFF 202 au nil := diob - a, ccl. 203 00E 8411FFFF 204 if LOW_SAME = 1 then goto duty_100, flush. 205 206 return, flush; 00F D9FF1FFF 207 chan clear flag0. 208 209 duty_0 : 210 au ert := sr + diob; 211 chan write_mer, neg_mrl,pin := low, pac := no_change; 212 chan set flag0; 213 chan cir; 010 545CF18A 214 end. 215 216 duty_100 : 217 au ert := sr + diob; 218 chan write_mer,neg_mrl,pin := high, pac := no_change; 219 chan set flag0; 220 chan cir; 011 545CF14A 221 end. 222 223 224 (**********************************************************************) 225 (* *) 226 (* STATE : Immed_H *) 227 (* *) 228 (* PRELOAD PARAMETER : OLDRIS *) 229 (* *) 230 (* ENTER WHEN : HSR11 is issued and pin is high *) 231 (* *) 232 (* ACTION : *) 233 (* 1.Init_cycle is called *) 234 (* 2.high_low match is generated on OLDRIS+PWMHI *) 235 (* 3.Interrupt request is asserted *) 236 (* *) 237 (**********************************************************************) 238 %entry start_address *; ram diob<-@OLDRIS; disable_match; 239 name = immed_h; 240 cond hsr1=0,hsr0=1,m/tsr=x,flag0=x,pin=1. 241 242 012 A406FFFF 243 if MRL = 1 then goto Normal_L_H, flush. (* Match pending? *) 244 013 D007FFFF 245 goto call_init_cycle, flush. 246 247 248 (**********************************************************************) 249 (* *) 250 (* STATE : Immed_L *) 251 (* *) 252 (* PRELOAD PARAMETER : OLDRIS *) 253 (* *) 254 (* ENTER WHEN : HSR11 is issued and pin is low *) 255 (* *) 256 (* ACTION : *) 257 (* 1.Init_cycle is called *) 258 (* 2.low to high match is generated on OLDRIS+PWMPER *) 259 (* 5.Interrupt request is asserted *) 260 (* *) 261 (**********************************************************************) 262 %entry start_address * ; ram diob<-@OLDRIS; disable_match; 263 name = immed_l; 264 cond hsr1=0,hsr0=1,m/tsr=x,flag0=x,pin=0. 265 266 014 A417FEFF 267 if MRL = 0 then goto Immed_L, flush. (* Match pending? *) 268 015 9C17FEFF 269 if flag0 = 0 then goto Immed_L, flush. (* Normal PWM? *) 270 (* Else, match pending and 0% or 100 % PWM so fall through *) 271 272 273 274 (**********************************************************************) 275 (* *) 276 (* STATE : Normal_0 *) 277 (* *) 278 (* PRELOAD PARAMETER : NONE *) 279 (* *) 280 (* ENTER WHEN : executing 0% duty cycle *) 281 (* (match occured and flag0 is set) *) 282 (* *) 283 (* ACTION : *) 284 (* 1.match time is stored into OLDRIS *) 285 (* 2.Init_cycle is called *) 286 (* 3.If not in level mode (init_cycle returns) *) 287 (* low to high match is generated on OLDRIS+PWMPER *) 288 (* 5.Interrupt request is asserted *) 289 (* *) 290 (**********************************************************************) 291 %entry start_address Normal_0; 292 name = normal_0; 293 cond hsr1=0,hsr0=0,m/tsr=1,flag0=1,pin=0,lsr=0. 294 295 Normal_0 : 296 au diob := ert; 016 3C7FF807 297 ram diob -> @OLDRIS. 298 299 Immed_L : 300 (* call init_cycle, match on oldris + pwmper *) 017 D409FFFF 301 Call Init_cycle, flush. 302 303 au ert := sr + diob; 304 chan write_mer, neg_mrl,pac := low_high; 305 chan cir; 018 545CF3FA 306 end. 307 308 309 (**********************************************************************) 310 (* *) 311 (* STATE : Normal_H_L *) 312 (* *) 313 (* PRELOAD PARAMETER : PWMRIS *) 314 (* *) 315 (* ENTER WHEN : high to low transition ocurred *) 316 (* *) 317 (* ACTION : *) 318 (* 1.low to high transition is generated on PWMRIS *) 319 (* *) 320 (**********************************************************************) 321 %entry start_address Normal_H_L; ram p<-@PWMRIS; 322 name = normal_h_l; 323 cond hsr1=0,hsr0=0,m/tsr=1,lsr=0,pin=0,flag0=0. 324 325 Normal_H_L : 326 au ert := p; 327 chan write_mer, neg_mrl,pac := low_high; 019 505DF3FE 328 end. 329 330 331 (**********************************************************************) 332 (* UNUSED ENTRIES - execute an end *) 333 (**********************************************************************) 334 %entry start_address End_of_Link; 335 name = pwm_undef; 336 cond hsr1=0,hsr0=0,lsr = 1. 337 338 %entry start_address End_of_phase; 339 name = pwm_undef; 340 cond hsr1=1,hsr0=1. 341 23 (* PWM 2.0 32 *) 24 %include 'uart.uc' ;function = $E. 41 42 (**********************************************************************) 43 (* *) 44 (* Function: UART Universal Asynchronous Receiver / Transmitter *) 45 (* *) 46 (* Creation Date: 27/Jul/92 From: NEW *) 47 (* *) 48 (* Author: Josef Fuchs / Ewald Liess *) 49 (* Change by xxxxxxxxx for ShortCut *) 50 (* Description: *) 51 (* ------------ *) 52 (* This function uses 1 or 2 TPU channels to form a uni or bidirection*) 53 (* UART. Baud rate is freely programmable by the user. The data word *) 54 (* length can be between 1 and 14 bits and no/odd/even parity is *) 55 (* supported. The function has been designed to operate in a similar *) 56 (* manner to the SCI port found on many Motorola MCUs. The function is*) 57 (* double buffered i.e there is a shift reg. and data reg. *) 58 (* All 16 TPU channels could be used for UART, each operating at more *) 59 (* than 9600 baud. *) 60 (* *) 61 (* Updates: By: Modification: *) 62 (* -------- --- ------------- *) 63 (* RevB JW Added interrupt generation to transmitter init *) 64 (* - state2 *) 65 (* 16/Jun/93 JW Moved receiver interrupt generation to be after *) 66 (* data write for correct polled operation. *) 67 (* Designated as rev 1.0 for mask release. *) 68 (* 12/Aug/93 JL Converted to new TPUMASM syntax *) 69 (* *) 70 (*--------------------------------------------------------------------*) 71 (* Standard Exits Used:- End_Of_Phase: N End_Of_Link: Y *) 72 (* *) 73 (* External Files included: NONE *) 74 (* *) 75 (* CODE SIZE excluding standard exits = 67 LONG WORDS *) 76 (*--------------------------------------------------------------------*) 77 (* *) 78 (* *) 79 (********** This Revision: 1.1 *********) 80 (* *) 81 (********** LAST MODIFIED: 12/Aug/93 BY: Jeff Loeliger ********) 82 (* *) 83 (**********************************************************************) 84 (***************************************************************************) 85 (*Motorola reserves the right to make changes without further notice to any*) 86 (*product herein. Motorola makes no warranty, representation or guarantee *) 87 (*regarding the suitability of its products for any particular purpose, nor*) 88 (*does Motorola assume any liability arising out of the application or use *) 89 (*of any product or circuit, and specifically disclaims any and all *) 90 (*liability, including without limitation consequential or incidental *) 91 (*damages. "Typical" parameters can and do vary in different applications. *) 92 (*All operating parameters, including "Typical",must be validated for each *) 93 (*customer application by customer's technical experts. Motorola does not *) 94 (*convey any license under its patent rights nor the rights of others. *) 95 (*Motorola products are not designed, intended, or authorized for use as *) 96 (*components in systems intended for surgical implant into the body, or *) 97 (*other applications intended to support or sustain life, or for any other *) 98 (*application in which the failure of the Motorola product could create a *) 99 (*situation where injury or death may occur. Should Buyer purchase or use *) 100 (*Motorola products for any such unintended or unauthorized application, *) 101 (*Buyer, shall indemnify and hold Motorola and its officers, employees, *) 102 (*subsidiaries, affiliates, and distributors harmless against all claims, *) 103 (*costs, damages, and expenses, and reasonable attorney fees arising out *) 104 (*of, directly or indirectly, any claim of personal injury or death *) 105 (*associated with such unintended or unauthorized use, even if such claim *) 106 (*alleges that Motorola was negligent regarding the design or manufacture *) 107 (*of the part. *) 108 (*Motorola and the Motorola logo are registered trademarks of Motorola Inc.*) 109 (*Motorola is an Equal Opportunity/Affirmative Action Employer. *) 110 (*Copyright Motorola Inc. 1993 *) 111 (***************************************************************************) 112 113 114 (*******************************************************) 115 (* 116 117 118 $CONSTANTS: 119 120 #define tpuc_UART_FUNCTION (0xF) 121 122 #define tpuc_UART_HSQ_NO_PARITY (0x00) 123 #define tpuc_UART_HSQ_EVEN_PARITY (0x02) 124 #define tpuc_UART_HSQ_ODD_PARITY (0x03) 125 126 127 #define tpuc_UART_HSR_NO_ACTION (0x00) 128 #define tpuc_UART_HSR_FORCE_TX_INTERRUPT (0x01) 129 #define tpuc_UART_HSR_INIT_RECEIVER (0x02) 130 #define tpuc_UART_HSR_INIT_TRANSMITTER (0x03) 131 132 133 $ 134 $TYPEDEFS: 135 136 typedef 137 enum { 138 tpuc_UART_PARITY_TEMP , 139 tpuc_UART_MATCH_RATE , 140 tpuc_UART_DATA , 141 tpuc_UART_DATA_SIZE , 142 tpuc_UART_ACTUAL_BIT_COUNT , 143 tpuc_UART_SHFT_REG 144 } tpuc_Uart_pram ; 145 146 147 /* 148 *()()()()()()()()() UART.UC : DATA STRUCTURE ()()()()()()()()()()()()* 149 * * 150 * name: Written By: Location Bits: * 151 * ----- ----------- --------------- * 152 * PARITY_TEMP TPU Parameter0 0..15 * 153 * Used by TPU to calculate parity - CPU must not * 154 * write. * 155 * * 156 * MATCH_RATE CPU Parameter1 0..15 * 157 * Baud period in TCR1 clocks. * 158 * * 159 * DATA BOTH Parameter2 0..15 * 160 * Transmit or Receive data register. For transmit* 161 * ,bit 15 must be 0. * 162 * * 163 * DATA_SIZE CPU Parameter3 0..7 * 164 * Holds the number of bits in a data word - * 165 * INCLUDING parity. * 166 * * 167 * CPU Parameter3 8..15 * 168 * Transmitter Datalocation for shortcut * 169 * If shortcut not used, set it to zero. * 170 * * 171 * ACTUAL_BIT_COUNT TPU Parameter4 0..15 * 172 * Used by the TPU to count the number of bits. * 173 * CPU must not write. * 174 * * 175 * SHIFT_REG TPU Parameter5 0..15 * 176 * Used by the TPU for shifting in/out data. * 177 * CPU must not write. * 178 * * 179 * * 180 * HSQ1 HSQ0 Action * 181 * ---- ---- ------ * 182 * 0 0 No Parity. * 183 * 0 1 No Parity. * 184 * 1 0 Even Parity. * 185 * 1 1 Odd Parity. * 186 * * 187 * hsr1 hsr0 Action * 188 * ---- ---- ------ * 189 * 0 0 No action * 190 * 0 1 Force interrupt * 191 * 1 0 Initialise channel as receiver. [clfg1 cleared]* 192 * 1 1 Initialise chan as transmitter. [cflg1 set] * 193 * * 194 * Links Accepted: NO Links Generated: NO * 195 * * 196 * Interrupts Generated After: Transmit data empty/receive data full* 197 * * 198 *()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()* 199 */ 200 201 $ 202 203 *) 204 (*********************************************************) 205 206 207 (*+++++++++++++++++++++ PARAMETER MACROS +++++++++++++++++++++++++++*) 208 209 %macro PARITY_TEMP_UART 'prm0'. 210 %macro MATCH_RATE_UART 'prm1'. 211 %macro DATA_UART 'prm2'. 212 %macro DATA_SIZE_UART 'prm3'. 213 %macro ACTUAL_BIT_COUNT_UART 'prm4'. 214 %macro SHFT_REG_UART 'prm5'. 215 216 (* conditions *) 217 %macro RECEIVER_UART 'flag1 = 0'. (* Receiver is selected by cflag1=0 *) 218 %macro PARITY_OFF_UART 'hsq1 = 0'. (* no Parity *) 219 %macro PARITY_EVEN_UART 'hsq0 = 0'. (* use even Parity *) 220 221 222 (*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*) 223 224 225 (*====================================================================*) 226 (*||||||||||||||||||||| MICROCODE STARTS BELOW |||||||||||||||||||||*) 227 (*VVVVVVVVVVVVVVVVVVVVV--------------------------VVVVVVVVVVVVVVVVVVVVV*) 228 229 230 231 (**********************************************************************) 232 (* *) 233 (* State 1: Initialisation for RECEIVER *) 234 (* *) 235 (* entered by HSR 2 *) 236 (**********************************************************************) 237 238 %entry start_address *;disable_match; 239 name = INIT_RECEIVER_UART; 240 cond hsr1 = 1, hsr0 = 0. 241 242 INIT_RECEIVER_UART: chan tbs := in_m1_c1, 243 pac := high_low; 244 chan clear flag0; (*wait for start-bit = falling edge *) 01A BFFF05C4 245 enable_mtsr. 246 247 chan neg_tdl, neg_mrl, neg_lsl; 248 chan clear flag1; (* select RECEIVER *) 01B 7FF9FED6 249 end. 250 251 252 253 (**********************************************************************) 254 (* *) 255 (* State 2: Initialisation for TRANSMITTER *) 256 (* *) 257 (* entered by HSR 3 *) 258 (**********************************************************************) 259 260 %entry ram p <- @MATCH_RATE_UART; start_address *;disable_match; 261 name = INIT_TRANSMIT_UART; 262 cond hsr1 = 1, hsr0 = 1. 263 264 INIT_TRANSMIT_UART: chan tbs := out_m1_c1, 265 pac := no_change, 266 pin := high; 267 chan clear flag0; (* poll the TDRE-bit *) 01C BFFF4144 268 enable_mtsr. 269 270 au ert := tcr1 + p; 271 chan neg_tdl, neg_mrl, neg_lsl; 272 write_mer; 273 chan set flag1; (* select TRANSMITTER *) 274 chan cir; (* revB - for IRQ driven transmitter *) 01D 58583EDA 275 end. 276 277 (**********************************************************************) 278 (* *) 279 (* State 2.1: Force_Interrupt *) 280 (* *) 281 (* entered by HSR 1 *) 282 (**********************************************************************) 283 284 %entry ram diob <- @DATA_UART;start_address *; 285 name = FORCE_INTERRUPT; 286 cond hsr1 = 0, hsr0 = 1. 287 288 FORCE_INTERRUPT: 01E 37FDFFFF 289 au nil := diob,ccl. 01F 8C01FEFF 290 if N = 0 then goto END_OF_LINK,flush. 291 chan cir; (* set IRQ for IRQ driven transmitter *) 020 7FFFFFFA 292 end. 293 294 295 296 (**********************************************************************) 297 (* *) 298 (* if TRANSMITTER then State 3: POLLING TDRE *) 299 (* else RECEIVER then goto STATE 5: FALLING EDGE DETECTED *) 300 (* *) 301 (* For Transmitter: *) 302 (* entered after a match if no data is sent out, then: *) 303 (* if TDRE is set: set up next match to test TDRE again *) 304 (* else set cflag0 to indicate transmittion and send startbit *) 305 (* *) 306 (* For Receiver: *) 307 (* entered after a falling edge (of startbit) is detected, *) 308 (* then goto State 5 (receive startbit) *) 309 (**********************************************************************) 310 311 %entry ram diob <- @MATCH_RATE_UART; start_address *; disable_match; 312 name = SERV_START_BIT_UART; 313 cond hsr1 = 0, hsr0 = 0, m/tsr = 1,lsr = 0, pin = x,flag0 = 0. 314 315 SERV_START_BIT_UART: 021 9A3DFEFF 316 if @RECEIVER_UART then goto RXD_START_BIT_UART. 317 (* Goto Receiver *) 318 319 au p := 0; 022 3EFFF003 320 ram p -> @PARITY_TEMP_UART. (* reset high-bit counter *) 321 322 (* following statements are for transmitter only *) 323 324 au ert := ert + diob; (* define first match *) 325 chan neg_mrl, neg_lsl, neg_tdl; 023 5C58FEFF 326 write_mer. 327 024 1FFFF00B 328 ram p <- @DATA_UART. 329 330 au nil := p, ccl; (* test TDRE *) 025 11FDF80F 331 ram diob <- @DATA_SIZE_UART. 332 026 8C01FFFF 333 if N = 1 then goto END_OF_LINK,flush. 334 335 (* valid data found, send it *) 336 337 SEND_START_BIT_UART: 338 chan pac := low; (* start bit *) 339 chan set flag0; (* now send data *) 027 7FFFF5CB 340 chan cir. 341 342 au diob := diob+1; (* count also startbit *) 028 367FD813 343 ram diob -> @ACTUAL_BIT_COUNT_UART. 344 345 au p := p + max; (* chan set TDRE-Bit = MSB *) 029 30FFC017 346 ram p -> @SHFT_REG_UART. (* copy data to shift register *) 347 348 ram p -> @DATA_UART; (* chan set TDRE in Dataword *) 02A 3FFFF00A 349 end. 350 351 352 353 (**********************************************************************) 354 (* *) 355 (* if TRANSMITTER then State 4: send data bits *) 356 (* else if RECEIVER then goto STATE 6: receive data bits *) 357 (* *) 358 (* Read the Data and shift the LSB-Bit out, then write the shifted *) 359 (* value into the SHFT_REG and decrement ACTUAL_BIT_COUNT. *) 360 (**********************************************************************) 361 362 %entry ram diob <- @MATCH_RATE_UART; start_address *; disable_match; 363 name = SERV_DATA_BITS_UART; 364 cond hsr1 = 0, hsr0 = 0, m/tsr = 1, lsr = 0, pin = x, flag0 = 1. 365 366 SERV_DATA_BITS_UART: 367 au ert := ert + diob; 02B 1C5EF013 368 ram p <- @ACTUAL_BIT_COUNT_UART. 369 02C 9A43FEFF 370 if @RECEIVER_UART then goto RXD_DATA_BIT_UART. 371 (* Goto Receiver *) 372 373 au p := p - 1, ccl; (* decrement number of bits *) 02D 30FDE013 374 ram p -> @ACTUAL_BIT_COUNT_UART. 375 376 (* following statements are for transmitter only *) 377 02E 8C3CFFFF 378 if N = 1 then goto SEND_STOP_BIT_UART,flush. 379 02F 9437FFFF 380 if Z = 1 then goto SEND_PARITY_UART,flush. 381 030 1FFFF017 382 ram p <- @SHFT_REG_UART. 383 031 1FFFF803 384 ram diob <- @PARITY_TEMP_UART. 385 386 SEND_BIT_UART: au p :=>> p, ccl; (* shift out data bit *) 032 30EDF017 387 ram p -> @SHFT_REG_UART. 388 033 9035FFFF 389 if C = 1 then goto SEND_HIGH_BIT_UART,flush. 390 391 SEND_LOW_BIT_UART: 392 chan pac := low; 393 neg_tdl, neg_lsl, neg_mrl; 394 write_mer; 034 5FF9F4FE 395 end. 396 397 SEND_HIGH_BIT_UART: 398 au diob:= diob+1; (* update parity *) 035 367FD803 399 ram diob -> @PARITY_TEMP_UART. 400 401 chan pac := high; 402 neg_tdl, neg_lsl, neg_mrl; 403 write_mer; 036 5FF9F2FE 404 end. 405 406 SEND_PARITY_UART: 037 AC3CFEFF 407 if @PARITY_OFF_UART then goto SEND_STOP_BIT_UART,flush. 408 038 B232FEFF 409 if @PARITY_EVEN_UART then goto SEND_BIT_UART. 410 039 1FFFF003 411 ram p <- @PARITY_TEMP_UART. 412 03A D232FFFF 413 goto SEND_BIT_UART. 414 03B 30FFDFFF 415 au p := p + 1. (* generate odd parity = do a complement *) 416 417 SEND_STOP_BIT_UART: 418 chan pac := high; 419 neg_tdl, neg_lsl, neg_mrl; 420 write_mer; 421 chan clear flag0; 03C 5FF9F2C6 422 end. 423 424 425 (**********************************************************************) 426 (* *) 427 (* STATE 5: FALLING EDGE DETECTED *) 428 (* *) 429 (* START-Bit and start sampling in the middle of a BIT *) 430 (* = set up a match after 1.5 bittimes *) 431 (* *) 432 (* Parity Temp already cleared, diob contains Matchrate *) 433 (* *) 434 (**********************************************************************) 435 436 RXD_START_BIT_UART: 437 au ert:=ert+diob; 03D 1C5EF00F 438 ram p <- @DATA_SIZE_UART. 03E 20FFFFFF 439 au p:=p_low. 03F AC41FEFF 440 if @PARITY_OFF_UART then goto RXD_NO_PARITY_UART,flush. 441 040 30FFDFFF 442 au p := p + 1. (* count also parity bit if enabled *) 443 444 RXD_NO_PARITY_UART: 445 ram p -> @ACTUAL_BIT_COUNT_UART; 041 366FF013 446 au diob :=>> diob. (* MATCHRATE/2 *) 447 448 au ert := ert + diob; (* ert := ert +1.5*Matchrate *) 449 chan pac := no_detect; chan set flag0; 450 neg_mrl, neg_lsl, neg_tdl; 451 write_mer; 042 5C58F0CE 452 end. 453 454 455 456 (**********************************************************************) 457 (* *) 458 (* STATE 6: RECEIVE BITS *) 459 (* *) 460 (* Read the value at the pin and shift this value in the SHFT_REG. *) 461 (* Also decrement ACTUAL_BIT_CNT (the number of received bits). *) 462 (* *) 463 (* diob contains Matchrate, ert already set up with ert+diob *) 464 (* no write_mer issued !! *) 465 (* Actual_Bit_Count is already decremented ccl set by decrement *) 466 (**********************************************************************) 467 468 RXD_DATA_BIT_UART: 043 8E4BFFFF 469 if N = 1 then goto RECEIVE_STOP_UART. 470 471 au a := 0; (* clear FLAG-BITS *) 044 1E1FF817 472 ram diob <- @SHFT_REG_UART. (* read shiftregister *) 473 474 (* there is a data bit to receive *) 475 045 B648FFFF 476 if psl = 1 then goto RECEIVE_HIGH_UART. 477 (* high bit has to be received *) 478 au diob :=>> diob; (* shift zero into BIT15 *) 479 chan neg_tdl, neg_lsl, neg_mrl; 046 5669FEFF 480 write_mer. 481 482 RECEIVE_LOW_UART: 483 ram diob -> @SHFT_REG_UART; (* get the low bit *) 047 3FFFF816 484 end. 485 486 RECEIVE_HIGH_UART: 487 au diob := diob + max; (* chan set received bit, shifted before *) 048 367FC817 488 ram diob -> @SHFT_REG_UART. 489 049 1FFFF803 490 ram diob <- @PARITY_TEMP_UART. (* add parity *) 491 492 au diob := diob + 1; (* count an additional high bit *) 493 ram diob -> @PARITY_TEMP_UART; 04A 367FD802 494 end. 495 496 (* all data bits have been received and stored left justified in the shift- *) 497 (* register if parity was enabled, parity is in BIT15 of the shift register *) 498 499 RECEIVE_STOP_UART: 04B B44DFFFF 500 if psl = 1 then goto RXD_OK_UART, flush. 501 (*stopbit must be high *) 502 04C 3E0FCFFF 503 SET_FE_FLAG_UART: au a :=>> max. 504 (* set Framing Error if stopbit was not high *) 505 (* stores $4000 into a, sets Bit 14 *) 506 507 (* now check the parity *) 508 RXD_OK_UART: 04D AC54FEFF 509 if @PARITY_OFF_UART then goto PAR_OK_UART,flush. 510 (* Parity enabled ? *) 511 512 au diob :=<< diob; (* remove Parity *) 04E 1667F003 513 ram p <- @PARITY_TEMP_UART. 514 04F B051FEFF 515 if @PARITY_EVEN_UART then goto EVEN_PAR_UART,flush. 516 050 30FFDFFF 517 au p := p + 1. (* for odd parity, negate it *) 518 051 31EDFFFF 519 EVEN_PAR_UART: au nil :=>> p,ccl. (* copy LSB from PARITY_TEMP to Carry *) 520 052 9054FEFF 521 if C = 0 then goto PAR_OK_UART,flush. 522 523 (* there was a parity error *) 053 321FCFFF 524 au a := a + max. (*set Parity error, $8000, Bit 15 chan set*) 525 526 (* now move the left justified value in the shiftregister to right *) 527 (* to have a right justified result *) 528 529 PAR_OK_UART: ram p <- @DATA_SIZE_UART; 054 00FFF00F 530 au p:=p_low. 531 (* calculate number of bits to shift right *) 532 533 au dec := dec - p; (* align to the right side *) 534 chan pac := high_low; (* init for new startbit *) 055 655805C7 535 chan clear flag0;neg_tdl,neg_mrl. 536 537 repeat; 056 366FFFFD 538 au diob :=>> diob. (* align data right *) 539 540 au diob := diob + a; (* combine data and flags *) 057 367E780B 541 ram diob -> @DATA_UART. (* and store received dataword *) 542 ram p <- @DATA_SIZE_UART ; 058 027DF00F 543 au diob := p_high;ccl. 059 965CFFFF 544 if Z=1 then goto END_RECIEVE . 545 546 ram p <- @DATA_UART; 05A 00FFF00B 547 au p:=p_low . 05B 3FFFF203 548 ram p -> by_diob . 549 550 END_RECIEVE : chan cir; (* generate RDRF-interrupt *) 05C 7FFFFFFA 551 end. 552 553 554 555 (**********************************************************************) 556 (* UNDEFINED ENTRIES - execute an end. *) 557 (**********************************************************************) 558 (*%entry start_address END_OF_LINK; *) 559 (*name = UART_UNDEF; *) 560 (*cond hsr1 = 0,hsr0 = 1. *) 561 562 %entry start_address END_OF_LINK; disable_match; 563 name = UART_UNDEF; 564 cond hsr1 = 0, hsr0 = 0, m/tsr = 0, lsr = 1, pin = x, flag0 = x. 565 566 %entry start_address END_OF_LINK; disable_match; 567 name = UART_UNDEF; 568 cond hsr1 = 0, hsr0 = 0, m/tsr = 1, lsr = 1, pin = x, flag0 = x. 24 25 %include 'iic.uc' ;function = $D. 1 (**********************************************************************) 2 (* *) 3 (* Function: IIC - IIC-Bus *) 4 (* *) 5 (* Creation Date: 24.6.98 From: PWM *) 6 (* *) 7 (* Author: A. Morbach *) 8 (* *) 9 (* Description: *) 10 (* ------------ *) 11 (* *) 12 (* name: Written By: Location Bits: *) 13 (* ----- ----------- --------------- *) 14 (* IIC_SLAVE_ADDRESS CPU Parameter0 8..15 *) 15 (* Slave adress of the IIC device which is HW decoded. *) 16 (* The last bit (LSB) defines if the following transfer *) 17 (* is read or write. See IIC specifications. *) 18 (* *) 19 (* IIC_BYTE_ADDRESS CPU Parameter0 0..7 *) 20 (* Byte address. Only the IIC device which was addressed *) 21 (* by the previous IIC_SLAVE_ADDRESS will use this *) 22 (* IIC_BYTE_ADDRESS. *) 23 (* *) 24 (* IIC_DATA CPU / TPU Parameter1 0..7 *) 25 (* In write mode this byte will be sent. In read mode the *) 26 (* received byte will be here to be read by CPU. *) 27 (* *) 28 (* IIC_SHIFT_REGISTER TPU Parameter2 0..7 *) 29 (* holds the data to be shifted out or in. *) 30 (* *) 31 (* IIC_COUNT TPU Parameter3 0..3 *) 32 (* is used to count SCL edges, to determin if *) 33 (* actual state is to be ended. *) 34 (* *) 35 (* IIC_CLK_LOW_TIME CPU Parameter4 0..15 *) 36 (* defines the minimum clock low time. The same *) 37 (* time is used as high time, which is normally *) 38 (* lower (about 4us instead of 4.7us as low time). *) 39 (* CLK_LOW_TIME must be 2 or greater. Even with *) 40 (* a very slow TCR1 CLK_LOW_TIME = 1 is not *) 41 (* allowed, because of the internal timing. The *) 42 (* really used time is between CLK_LOW_TIME - 1 and *) 43 (* CLK_LOW_TIME. So 1 could degrade to 0, which *) 44 (* would be too fast. *) 45 (* *) 46 (* IIC_STATE CPU / TPU Parameter5 0..15 *) 47 (* The transmission of bits over the IIC bus is *) 48 (* divided into several states. The actual state *) 49 (* is stored in the lower byte of STATE. To see *) 50 (* how the states are coded, see the table *) 51 (* following this header. *) 52 (* The high byte of STATE gives a status of *) 53 (* operation. It is to be reset before starting a *) 54 (* transmission. *) 55 (* STATE(8..15) = 0x00: transmission in progress. *) 56 (* STATE(8..15) = 0x80: transmission is complete *) 57 (* without error. *) 58 (* STATE(8..15) = 0x81: transmission is complete *) 59 (* with error: missing *) 60 (* acknowledge. *) 61 (* *) 62 (* HSQ1 HSQ0 Action *) 63 (* ---- ---- ------ *) 64 (* x x HSQ is not used *) 65 (* *) 66 (* HSR1 HSR0 Action *) 67 (* ---- ---- ------ *) 68 (* 0 1 Initiate transfer *) 69 (* 1 0 No action *) 70 (* 1 1 Initialize ports *) 71 (* *) 72 (* flag1 1: Read operation of IIC device *) 73 (* 0: Write operation of IIC device *) 74 (* *) 75 (* flag0 1: Data IO is under way *) 76 (* 0: Control bits are generated *) 77 (* *) 78 (* Links Accepted: NO Links Generated: NO *) 79 (* *) 80 (* Interrupts Generated After: Each complete transfer *) 81 (* *) 82 (* *) 83 (* Every state (stored in IIC_STATE) begins with SCL = 0. *) 84 (* *) 85 (* flag1 = 1 (read) | flag1 = 0 (write) *) 86 (* --------------------------------------------------------------------------- *) 87 (* State by name | IIC_STATE | flag0 | State by name | IIC_STATE | flag0 *) 88 (* --------------------------------------------------------------------------- *) 89 (* SLAVE_ADR_OUT | 03 | 1 | SLAVE_ADR_OUT | 03 | 1 *) 90 (* REC_ACKNOWLEDGE | 03 | 0 | REC_ACKNOWLEDGE | 03 | 0 *) 91 (* --------------------------------------------------------------------------- *) 92 (* BYTE_ADR_OUT | 05 | 1 | BYTE_ADR_OUT | 05 | 1 *) 93 (* REC_ACKNOWLEDGE | 05 | 0 | REC_ACKNOWLEDGE | 05 | 0 *) 94 (* --------------------------------------------------------------------------- *) 95 (* START_CONDITION | 40 | 0 | | | *) 96 (* --------------------------------------------------------------------------- *) 97 (* SLAVE_ADR_OUT | 09 | 1 | DATA_OUT | 09 | 1 *) 98 (* REC_ACKNOWLEDGE | 09 | 0 | REC_ACKNOWLEDGE | 09 | 0 *) 99 (* --------------------------------------------------------------------------- *) 100 (* DATA_IN | 80 | 1 | | | *) 101 (* SEND_NO_ACK | 80 | 0 | | | *) 102 (* --------------------------------------------------------------------------- *) 103 (* STOP_CONDITION | 20 | 0 | STOP_CONDITION | 20 | 0 *) 104 (* *) 105 (* *) 106 (* *) 107 (* START_CONDITION: *) 108 (* *) 109 (* ---+ +--------------------- *) 110 (* SCL | | *) 111 (* +----------+ *) 112 (* *) 113 (* +++++-------------------+ *) 114 (* SDA + | *) 115 (* +++++ +----------- *) 116 (* *) 117 (* ^ ^ ^ *) 118 (* | | +-- 2. IIC_RIS_CT: SDA Output Low *) 119 (* | | *) 120 (* | +------------ 1. IIC_RIS_CT: SDA Output High *) 121 (* | *) 122 (* +----------------------- IIC_FAL_CT: SDA Output High *) 123 (* *) 124 (* Next state is 09 with flag0 = 1. *) 125 (* *) 126 (* *) 127 (* *) 128 (* STOP_CONDITION: *) 129 (* *) 130 (* ---+ +--------------------- *) 131 (* SCL | | *) 132 (* +----------+ *) 133 (* *) 134 (* +++++ +----------- *) 135 (* SDA + | *) 136 (* +++++-------------------+ *) 137 (* *) 138 (* ^ ^ ^ *) 139 (* | | +-- 2. IIC_RIS_CT: SDA Output High *) 140 (* | | *) 141 (* | +------------ 1. IIC_RIS_CT: SDA Output Low *) 142 (* | *) 143 (* +----------------------- IIC_FAL_CT: SDA Output Low *) 144 (* *) 145 (* There is no next state, no further matches are set up. STATUS = 80 *) 146 (* *) 147 (* *) 148 (* *) 149 (* SEND_NO_ACK: *) 150 (* *) 151 (* ---+ +----- *) 152 (* SCL | | *) 153 (* +----------+ *) 154 (* *) 155 (* +++++--------------- *) 156 (* SDA + *) 157 (* +++++ *) 158 (* *) 159 (* ^ ^ *) 160 (* | +------------ IIC_RIS_CT: SDA Output High *) 161 (* | *) 162 (* +----------------------- IIC_FAL_CT: SDA Output High *) 163 (* *) 164 (* Next state is 20 with flag0 = 0. *) 165 (* *) 166 (* *) 167 (* *) 168 (* REC_ACKNOWLEDGE: *) 169 (* *) 170 (* ---+ +----- *) 171 (* SCL | | *) 172 (* +----------+ *) 173 (* *) 174 (* +++++----------+---- *) 175 (* SDA + + *) 176 (* +++++----------+---- *) 177 (* *) 178 (* ^ ^ *) 179 (* | +------------ IIC_RIS_CT: SDA checked if low *) 180 (* | *) 181 (* +----------------------- IIC_FAL_CT: SDA Input *) 182 (* *) 183 (* If SDA is high, then STATUS = ???. No further matches. *) 184 (* If SDA is low then next state depends on current state and flag1. *) 185 (* *) 186 (* current state | flag1 | next state and flag0 *) 187 (* ---------------------------------------------- *) 188 (* 03 | 1 | 05 1 *) 189 (* 03 | 0 | 05 1 *) 190 (* 05 | 1 | 40 0 *) 191 (* 05 | 0 | 09 1 *) 192 (* 09 | 1 | 80 1 *) 193 (* 09 | 0 | 20 0 *) 194 (* *) 195 196 %macro IIC_ADDRESS 'prm0'. 197 %macro IIC_DATA 'prm1'. 198 %macro IIC_SHIFT_REGISTER 'prm2'. 199 %macro IIC_COUNT 'prm3'. 200 %macro IIC_CLK_LOW_TIME 'prm4'. 201 %macro IIC_STATE 'prm5'. 202 203 %macro IIC_BIT_START '#$C0'. 204 %macro IIC_BIT_STOP '#$20'. 205 %macro IIC_BIT_NOACK '#$C0'. 206 207 (************************************************************************) 208 (* *) 209 (* ENTRY name: IIC_INIT *) 210 (* *) 211 (* PRELOAD PARAMETER : IIC_ADDRESS *) 212 (* *) 213 (* ENTER WHEN : HSR = %11 *) 214 (* *) 215 (* ACTION: Initialize portpins, SCL high, SDA high. *) 216 (* Don't activate any matches. *) 217 (************************************************************************) 218 %entry start_address *; ram p<-@IIC_ADDRESS; disable_match; name = IIC_INIT; 219 cond hsr1=1,hsr0=1. 220 221 IIC_INIT: 222 (* drive SCL high. SCL should already be high due to external pullup *) 223 chan pin := high, TBS := out_m1_c1, PAC := no_change, 05D BFFF417D 224 disable_mtsr. 225 05E E73E21FF 226 au chan_reg := chan_reg + #$10. (* change to Channel SDA *) 227 05F FFFFFFFF 228 nop. (* wait for next channel *) 229 230 231 (* drive SDA high. Since SDA is externally coupled by a diode, *) 232 (* the bus will be high due to external pullup *) 060 BFFF417D 233 chan pin := high, TBS := out_m1_c1, PAC := no_change; disable_mtsr. 234 061 3FFFFFFE 235 end. 236 237 (************************************************************************) 238 (* *) 239 (* ENTRY name: IIC_START_TRANSFER *) 240 (* *) 241 (* PRELOAD PARAMETER : IIC_ADDRESS *) 242 (* *) 243 (* ENTER WHEN : HSR = %01 *) 244 (* *) 245 (* ACTION: *) 246 (* Initiate Transfer *) 247 (* Load IIC_SHIFT_REGISTER with IIC_ADRESS. Clear R/W bit in *) 248 (* IIC_SHIFT_REGISTER because the first transmission is always a *) 249 (* write to the IIC device. *) 250 (* Store read or write operation in flag1. *) 251 (* Set IIC_STATE to 03. *) 252 (* Set IIC_COUNT to 8 for 8 bit transmission. *) 253 (* Set flag0 to 1 to transmit data. *) 254 (* Generate Start Condition by setting SDA to low while SCL is *) 255 (* high. *) 256 (* *) 257 (* Set up match time for falling SCL edge. *) 258 (************************************************************************) 259 %entry start_address *; ram p<-@IIC_ADDRESS; disable_match; 260 name = IIC_START_TRANSFER; 261 cond hsr1=0, hsr0=1. 262 263 264 IIC_START_TRANSFER: 265 au p_high :=>> p_high, ccl; (* RW bit into carry flag *) 062 E28C01CF 266 chan set flag0. (* begin with data transmission *) 267 063 2287FFFF 268 au p_high :=<< p_high. (* Back again. RW bit is now 0 *) 269 (* Every transmission begins with RW=0 *) 064 3FFFF00B 270 ram p -> @IIC_SHIFT_REGISTER. (* load shift register *) 271 272 if C = 0 then goto IIC_START_WRITE, flush; (* set flag1 if RW bit is 1 *) 065 90674ED4 273 chan tbs := out_m1_c1; enable_mtsr, clear flag1. 274 275 IIC_START_READ: 066 7FFFFFDF 276 chan set flag1. (* RW bit is 1: set flag1 *) 277 278 IIC_START_WRITE: 067 FEFE07FF 279 au p := #$03. (* state 03 at the beginning *) 280 281 IIC_START_CONT: 068 3FFFF017 282 ram p -> @IIC_STATE. (* state machine begins with 03 to send slave address *) 283 069 E73E21FF 284 au chan_reg := chan_reg + #$10. (* change to next channel, SDA *) 285 06A FEFE11FF 286 au p := #8. (* 8 bits to be sent *) 287 288 (* SDA is low, Start condition *) 06B BFFF41BD 289 chan pin := low, tbs := out_m1_c1, pac := no_change; disable_mtsr. 290 06C E73FE1FF 291 au chan_reg := chan_reg + #$F0. (* Back to SCL *) 292 293 ram p -> @IIC_COUNT; 06D D0DBF00F 294 goto IIC_NEXT_EDGE_LOW, flush. 295 296 (************************************************************************) 297 (* ENTRY name: IIC_FAL_IO *) 298 (* PRELOAD PARAMETER : IIC_STATE *) 299 (* ENTER WHEN : HSR = %00 *) 300 (* SCL = 0 *) 301 (* flag0 = 1 (Data bits) *) 302 (* ACTION: *) 303 (* A falling edge of SCL occured. Data bit has to be processed. *) 304 (* If state is 80 (DATA_IN) just a match for the next rising edge *) 305 (* has to be set up. *) 306 (* Otherwise the msb of the shift register is output at SDA. *) 307 (* *) 308 (* Set up match time for rising SCL edge. *) 309 (************************************************************************) 310 %entry start_address *; ram p <- @IIC_STATE; 311 name = IIC_FAL_IO; 312 cond hsr1 = 0, hsr0 = 0, lsr = 0, m/tsr = 1, pin = 0, flag0 = 1. 313 314 IIC_FAL_IO: 06E 20C5FFFF 315 au p_low :=<< p_low, ccl. (* get msb into C *) 316 06F 94DAFFFF 317 if Z = 1 then goto IIC_NEXT_EDGE_HIGH, flush. (* STATE = 80: do nothing *) 318 (* SDA is already in input mode, because *) 319 (* of acknowledge check. *) 320 321 IIC_FAL_OUT: 322 (* STATE = 03, 05 or 09. The msb of the shift register should be put out at SDA *) 070 1FFFF80B 323 ram diob <- @IIC_SHIFT_REGISTER. (* get shift register into diob *) 324 071 E73E21FF 325 au chan_reg := chan_reg + #$10. (* switch to SDA *) 326 072 3665FFFF 327 au diob :=<< diob, ccl. (* get msb into C *) 328 329 if C = 0 then goto IIC_FAL_OUT_LOW; 073 92764EFF 330 chan tbs := out_m1_c1. (* set pin to output *) 331 074 7FFFF1BF 332 chan pin := low, pac := no_change. (* Pin is low. No matter what C is *) 333 334 IIC_FAL_OUT_HI: 075 7FFFFF7F 335 chan pin := high. (* If C=0 this is not executed *) 336 337 IIC_FAL_OUT_LOW: 076 E73FE1FF 338 au chan_reg := chan_reg + #$F0. (* switch back to SCL *) 339 340 ram diob -> @IIC_SHIFT_REGISTER; (* store shift register *) 077 D0DAF80B 341 goto IIC_NEXT_EDGE_HIGH, flush. (* set up next edge *) 342 343 (************************************************************************) 344 (* ENTRY name: IIC_RIS_IO *) 345 (* STATE(S) ENTERED: *) 346 (* PRELOAD PARAMETER : *) 347 (* ENTER WHEN : HSR = %00 *) 348 (* SCL = 1 *) 349 (* flag0 = 1 (Data bits) *) 350 (* ACTION: *) 351 (* A rising edge of SCL occured. Data bit has to be processed. *) 352 (* If state is 80 (DATA_IN) the pin state of SDA is stored into the*) 353 (* lsb of IIC_SHIFT_REGISTER, which has been shiftet left before. *) 354 (* If state is 03, 05 or 09 nothing special has to be done. *) 355 (* In all modes IIC_COUNT is decremented. If IIC_COUNT reaches 0 *) 356 (* a switch to the next state is performed. *) 357 (* Otherwise the msb of the shift register is output at SDA. *) 358 (* *) 359 (* Set up match time for rising SCL edge. *) 360 (************************************************************************) 361 %entry start_address *; ram p <- @IIC_STATE; 362 name = IIC_RIS_IO; 363 cond hsr1 = 0, hsr0 = 0, lsr = 0, m/tsr = 1, pin = 1, flag0 = 1. 364 365 IIC_RIS_IO: 078 20C5FFFF 366 au p_low :=<< p_low, ccl. (* get away with msb *) 367 079 9481FEFF 368 if Z = 0 then goto IIC_RIS_OUT, flush. (* STATE = 03, 05 or 09: goto output mode *) 369 (* do nothing with shift register *) 370 371 IIC_RIS_INP: 07A 1FFFF80B 372 ram diob <- @IIC_SHIFT_REGISTER. (* get shift register into diob *) 373 07B E73E21FF 374 au chan_reg := chan_reg + #$10. (* switch to SDA *) 375 07C 3667FFFF 376 au diob :=<< diob. (* get ready to insert lsb *) 377 07D B47FFEFF 378 if psl = 0 then goto IIC_RIS_INP_LO, flush. 379 07E 367FDFFF 380 au diob := diob + 1. (* set lsb since the pin is high *) 381 382 IIC_RIS_INP_LO: 07F E73FE1FF 383 au chan_reg := chan_reg + #$F0. (* switch back to SCL *) 384 080 3FFFF80B 385 ram diob -> @IIC_SHIFT_REGISTER. (* store new data into shift register *) 386 387 IIC_RIS_OUT: 081 1FFFF00F 388 ram p <- @IIC_COUNT. (* get counter into p *) 389 390 au p := p - 1, ccl; (* decrement bit count *) 082 30FDE00F 391 ram p -> @IIC_COUNT. (* store bit count *) 392 083 94DBFEFF 393 if Z = 0 then goto IIC_NEXT_EDGE_LOW, flush. (* if not Z there are still *) 394 (* bits to be tranfered *) 395 396 (* All bits have been transfered. Now we have to switch to the handling of ack, start or stop. *) 084 1FFFF017 397 ram p <- @IIC_STATE. 398 399 au p_low :=<< p_low, ccl; 085 00C5F80B 400 ram diob <- @IIC_SHIFT_REGISTER. (* received data into diob *) 401 086 948BFEFF 402 if Z = 0 then goto IIC_RIS_RECACK, flush. (* In state 03, 05 and 09 acknowledge has *) 403 (* to be received. *) 404 405 IIC_RIS_NOACK: 406 (* in state 80 no acknowledge is to be sent out. *) 087 3FFFF807 407 ram diob -> @IIC_DATA. (* store received data into IIC_DATA *) 408 088 FE9F81FF 409 au p_high := @IIC_BIT_NOACK. 410 411 ram p -> @IIC_SHIFT_REGISTER; (* set up bit pattern for stop condition *) 089 3E7FD00B 412 au diob := 1. (* 1 rising edge *) 413 08A 3FFFF80F 414 ram diob -> @IIC_COUNT. 415 416 IIC_RIS_RECACK: 417 if TRUE then goto IIC_NEXT_EDGE_LOW, flush; (* setup next edge *) 08B BCDBFEC7 418 chan clear flag0. (* control bit is following, state keeps the same *) 419 420 (************************************************************************) 421 (* ENTRY name: IIC_FAL_CT *) 422 (* STATE(S) ENTERED: *) 423 (* PRELOAD PARAMETER : *) 424 (* ENTER WHEN : HSR = %00 *) 425 (* SCL = 0 *) 426 (* flag0 = 0 (Control bits: ack, start or stop) *) 427 (* ACTION: *) 428 (* A falling edge of SCL occured. Control bit has to be processed. *) 429 (* If state is 03, 05 or 09, SDA is set to input. *) 430 (* if state is 20, 40 or 80, the msb of the shift register is put *) 431 (* out at SDA. *) 432 (* *) 433 (* Set up match time for rising SCL edge. *) 434 (************************************************************************) 435 %entry start_address *; ram p <- @IIC_STATE; name = IIC_FAL_CT; 436 cond hsr1 = 0, hsr0 = 0, lsr = 0, m/tsr = 1, pin = 0, flag0 = 0. 437 438 IIC_FAL_CT: 08C 20CDFFFF 439 au p_low :=>> p_low, ccl. 440 08D 9092FEFF 441 if C = 0 then goto IIC_FAL_CT_STSTNOACK, flush. (* STATE = 80, 40 or 20: *) 442 443 IIC_FAL_CT_ACK: 444 (* with the states 03, 05 and 09, the reception of the acknowledge bit is to be *) 445 (* arranged. SDA is to be switched to input. *) 446 08E E73E21FF 447 au chan_reg := chan_reg + #$10. (* switch to SDA *) 448 08F BFFF01FF 449 chan tbs := in_m1_c1, pac := no_detect. (* SDA to input *) 450 090 E73FE1FF 451 au chan_reg := chan_reg + #$F0. (* switch back to SCL *) 452 091 D0DAFFFF 453 goto IIC_NEXT_EDGE_HIGH, flush. (* do nothing, just generate rising edge *) 454 455 IIC_FAL_CT_STSTNOACK: 456 (* With all three states 20, 40 and 80, the content of the shift register is to be *) 457 (* put out at SDA *) 092 1FFFF00B 458 ram p <- @IIC_SHIFT_REGISTER. 459 093 E73E21FF 460 au chan_reg := chan_reg + #$10. (* switch to SDA *) 461 094 30E5FFFF 462 au p :=<< p, ccl. (* set C with msb *) 463 464 465 if C = 0 then goto IIC_FAL_CT_LO_OUT, flush; 095 909740BF 466 chan tbs := out_m1_c1, pac := no_change, pin := low. (* SDA to output *) 467 096 7FFFFF7F 468 chan pin := high. 469 470 IIC_FAL_CT_LO_OUT: 097 E73FE1FF 471 au chan_reg := chan_reg + #$F0. (* switch back to SCL *) 472 473 ram p -> @IIC_SHIFT_REGISTER; (* store new value into shift register *) 098 D0DAF00B 474 goto IIC_NEXT_EDGE_HIGH, flush. (* do nothing, just generate rising edge *) 475 476 (************************************************************************) 477 (* *) 478 (* ENTRY name: IIC_RIS_CT *) 479 (* *) 480 (* STATE(S) ENTERED: *) 481 (* *) 482 (* PRELOAD PARAMETER : IIC_COUNT *) 483 (* *) 484 (* ENTER WHEN : HSR = %00 *) 485 (* SCL = 1 *) 486 (* flag0 = 0 (Control bits: ack, start or stop) *) 487 (* ACTION: *) 488 (* A rising edge of SCL occured or this is the second match with *) 489 (* SCL high (start or stop). Control bit has to be processed. *) 490 (* With SCL high (start, stop: 2. match) the next state has to be *) 491 (* determined. A lot of decisions have to be made. They are *) 492 (* explained in the code section. *) 493 (* flag0, IIC_SHIFT_REGISTER, IIC_COUNT and IIC_STATE are set up *) 494 (* for the beginning of the next state. *) 495 (* *) 496 (* Set up match time for rising SCL edge. *) 497 (************************************************************************) 498 %entry start_address *; ram p <- @IIC_STATE; 499 name = IIC_RIS_CT; 500 cond hsr1 = 0, hsr0 = 0, lsr = 0, m/tsr = 1, pin = 1, flag0 = 0. 501 502 IIC_RIS_CT: 503 au p_low :=>> p_low, ccl; (* Shift lsb into C *) 099 00CDF80F 504 ram diob <- @IIC_COUNT. (* get Count into diob *) 505 09A 90B9FFFF 506 if C = 1 then goto IIC_RIS_CT_ACK, flush. (* STATE = 03, 05 or 09 *) 507 508 IIC_RIS_CT_STSTNOACK: 509 (* STATE = 20, 40 or 80 *) 09B 1FFFF00B 510 ram p <- @IIC_SHIFT_REGISTER. (* get Shift register *) 511 09C E73E21FF 512 au chan_reg := chan_reg + #$10. (* switch to SDA *) 513 09D 30E5FFFF 514 au p :=<< p, ccl. (* set C with msb *) 515 516 (* at this output are no glitches allowed, because SCL is already high. With SCL high, *) 517 (* there are no unwanted edges at SDA allowed.*) 518 chan tbs := out_m1_c1, pac := no_change; (* SDA to output *) 09E 90A040FF 519 if C = 0 then goto IIC_RIS_CT_LO_OUT, flush. 520 521 chan pin := high; 09F BCA1FE7F 522 if TRUE then goto IIC_RIS_CT_CONT, flush. 523 524 IIC_RIS_CT_LO_OUT: 0A0 7FFFFFBF 525 chan pin := low. 526 527 IIC_RIS_CT_CONT: 0A1 E73FE1FF 528 au chan_reg := chan_reg + #$F0. (* switch back to SCL *) 529 530 au diob := diob - 1, ccl; (* decrement COUNT *) 0A2 367DE00B 531 ram p -> @IIC_SHIFT_REGISTER. (* store new value into shift register *) 532 0A3 3FFFF80F 533 ram diob -> @IIC_COUNT. (* store IIC_COUNT *) 534 0A4 94DAFEFF 535 if Z = 0 then goto IIC_NEXT_EDGE_HIGH, flush. (* still one edge left *) 536 0A5 1FFFF017 537 ram p <- @IIC_STATE. (* get state *) 538 0A6 20C5FFFF 539 au p_low :=<< p_low, ccl. 540 0A7 94ADFFFF 541 if Z = 1 then goto IIC_RIS_CT_NOACK, flush. (* STATE = 80 *) 542 0A8 20C5FFFF 543 au p_low :=<< p_low, ccl. 544 0A9 94B2FFFF 545 if Z = 1 then goto IIC_RIS_CT_START, flush. (* STATE = 40 *) 546 547 IIC_RIS_CT_STOP: 548 (* STATE = 20 *) 549 au p := $8000; 0AA 3EFFC017 550 ram p -> @IIC_STATE. (* STATE = 80: end of transmission, no errors *) 551 0AB BFFFFFFD 552 chan disable_mtsr. (* no further matches *) 553 554 chan cir; (* generate interrupt *) 0AC 7FFFFFFA 555 end. 556 557 IIC_RIS_CT_NOACK: 558 (* STATE = 80 *) 0AD FE9E41FF 559 au p_high := @IIC_BIT_STOP. 560 0AE 3FFFF00B 561 ram p -> @IIC_SHIFT_REGISTER. (* set up bit pattern for stop condition *) 562 0AF FEFE41FF 563 au p := #$20. (* next state will be 20 *) 564 0B0 FE7E05FF 565 au diob := #2. (* 2 rising edges *) 566 0B1 D0B6FFFF 567 goto IIC_RIS_CT_SETUP, flush. (* with p and diob set, goto setup *) 568 569 IIC_RIS_CT_START: 570 (* STATE = 40 *) 0B2 1FFFF003 571 ram p <- @IIC_ADDRESS. (* get slave address into p *) 572 0B3 3FFFF00B 573 ram p -> @IIC_SHIFT_REGISTER. (* and then into SHIFT_REGISTER *) 574 575 au p := #$09; (* next state is 09 *) 0B4 FEFE13CF 576 chan set flag0. (* data IO *) 577 578 IIC_RIS_CT_SETUP8: 0B5 FE7E11FF 579 au diob := #8. (* 8 bits to be sent *) 580 581 IIC_RIS_CT_SETUP: 582 (* The registers IIC_STATE and IIC_COUNT are loaded with the values of p and diob *) 0B6 3FFFF017 583 ram p -> @IIC_STATE. (* store next state *) 584 0B7 3FFFF80F 585 ram diob -> @IIC_COUNT. (* store count *) 586 0B8 D0DBFFFF 587 goto IIC_NEXT_EDGE_LOW, flush. (* next time it will be a falling edge *) 588 589 IIC_RIS_CT_ACK: 590 (* STATE = 03, 05 or 09 *) 591 (* p_low is 01 02 or 08 depending on the current state (03, 05 09) *) 0B9 E73E21FF 592 au chan_reg := chan_reg + #$10. (* switch to SDA *) 593 0BA 20CFFFFF 594 au p_low :=>> p_low. (* shift state right *) 595 0BB B4D5FFFF 596 if psl = 1 then goto IIC_RIS_CT_RECNOACK, flush. (* SDA = 1: No Ack *) 597 598 IIC_RIS_CT_RECACK: 0BC E73FE1FF 599 au chan_reg := chan_reg + #$F0. (* switch back to SCL *) 600 0BD 20CDFFFF 601 au p_low :=>> p_low, ccl. (* shift state right, the second time *) 602 0BE 90CAFFFF 603 if C = 1 then goto IIC_RIS_CT_BYT, flush. (* STATE = 05 *) 604 0BF 94C8FFFF 605 if Z = 1 then goto IIC_RIS_CT_FIRSLV, flush. (* STATE = 03 *) 606 607 IIC_RIS_CT_SECSLV: 608 (* STATE = 09 *) 0C0 98C3FEFF 609 if flag1 = 0 then goto IIC_RIS_CT_DATA, flush. (* STATE = 09, flag1 = 0 *) 610 611 (* STATE = 09, flag1 = 1 *) 612 au p := #$80; (* next state is 80 *) 0C1 FEFF01CF 613 chan set flag0. (* data IO *) 614 0C2 D0B5FFFF 615 goto IIC_RIS_CT_SETUP8, flush. (* store IIC_STATE and IIC_COUNT *) 616 617 IIC_RIS_CT_DATA: 618 (* STATE = 09, flag1 = 0 *) 0C3 FE9E41FF 619 au p_high := @IIC_BIT_STOP. 620 0C4 3FFFF00B 621 ram p -> @IIC_SHIFT_REGISTER. (* set up bit pattern for stop condition *) 622 0C5 FEFE41FF 623 au p := #$20. (* next state is 20 *) 624 0C6 FE7E05FF 625 au diob := #2. (* 2 rising edges *) 626 0C7 D0B6FFFF 627 goto IIC_RIS_CT_SETUP, flush. (* store IIC_STATE and IIC_COUNT *) 628 629 IIC_RIS_CT_FIRSLV: 630 (* STATE = 03 *) 631 au p := #$05; (* next state is 05 *) 0C8 FEFE0BCF 632 chan set flag0. (* data IO *) 633 0C9 D0B5FFFF 634 goto IIC_RIS_CT_SETUP8, flush. (* store IIC_STATE and IIC_COUNT *) 635 636 IIC_RIS_CT_BYT: 637 (* STATE = 05 *) 0CA 98D0FEFF 638 if flag1 = 0 then goto IIC_RIS_CT_DATA_OUT, flush. (* STATE = 05, flag1 = 0 *) 639 640 IIC_RIS_CT_START_COND: 641 (* STATE = 05, flag1 = 1 *) 0CB FE9F81FF 642 au p_high := @IIC_BIT_START. 643 0CC 3FFFF00B 644 ram p -> @IIC_SHIFT_REGISTER. (* set up bit pattern for stop condition *) 645 0CD FEFE81FF 646 au p := #$40. (* next state is 40 *) 647 0CE FE7E05FF 648 au diob := #2. (* 2 rising edges *) 649 0CF D0B6FFFF 650 goto IIC_RIS_CT_SETUP, flush. (* store IIC_STATE and IIC_COUNT *) 651 652 IIC_RIS_CT_DATA_OUT: 653 (* STATE = 05, flag1 = 0 *) 0D0 1FFFF007 654 ram p <- @IIC_DATA. (* get data byte into p_high *) 655 0D1 209FFFFF 656 au p_high := p_low. (* get low byte into high byte *) 657 0D2 3FFFF00B 658 ram p -> @IIC_SHIFT_REGISTER. (* and store it in IIC_SHIFT_REGISTER *) 659 660 au p := #$09; (* next state is 09 *) 0D3 FEFE13CF 661 chan set flag0. (* data IO *) 662 0D4 D0B5FFFF 663 goto IIC_RIS_CT_SETUP8, flush. (* store IIC_STATE and IIC_COUNT *) 664 665 IIC_RIS_CT_RECNOACK: 666 (* still in SDA channel *) 0D5 E73FE1FF 667 au chan_reg := chan_reg + #$F0. (* switch back to SCL *) 668 0D6 FE9F03FF 669 au p_high := #$81. (* end with error bit set *) 670 0D7 3FFFF017 671 ram p -> @IIC_STATE. (* STATE = 81: end of transmission *) 672 (* error: missing acknowledge *) 673 0D8 BFFFFFFD 674 chan disable_mtsr. 675 676 chan cir; (* generate interrupt *) 0D9 7FFFFFFA 677 end. 678 679 (**********************************************************************) 680 (**********************************************************************) 681 IIC_NEXT_EDGE_HIGH: 682 chan pac := high; 0DA BCDCF2FF 683 if TRUE then goto IIC_SET_NEXT_EDGE, flush. 684 685 IIC_NEXT_EDGE_LOW: 0DB 7FFFF5FF 686 chan pac := low. 687 688 IIC_SET_NEXT_EDGE: 689 au ert := tcr1; 0DC 185FF813 690 ram diob <- @IIC_CLK_LOW_TIME. 691 692 au ert := ert + diob; 0DD 5C58FEFF 693 chan write_mer, neg_lsl, neg_tdl, neg_mrl. 694 0DE FFFFFFFF 695 nop. 696 0DF 3FFFFFFE 697 end. 698 699 (**********************************************************************) 700 (**********************************************************************) 701 702 %entry start_address End_of_Link; 703 name = pwm_undef; 704 cond hsr1=0,hsr0=0, lsr = 1, m/tsr = 0. 705 706 %entry start_address End_of_Link; 707 name = pwm_undef; 708 cond hsr1=0,hsr0=0, lsr = 1, m/tsr = 1. 709 710 %entry start_address End_of_Link; 711 cond hsr1=1,hsr0=0. 712 25 1E8 0062 0062 IIC_START_TRANSFER IIC_START_TRANSFER 1E9 FE01 005D IIC_INIT 1EA B08C B06E IIC_FAL_CT IIC_FAL_IO 1EB B099 B078 IIC_RIS_CT IIC_RIS_IO 1EC FE01 FE01 pwm_undef pwm_undef 1ED FE01 FE01 pwm_undef pwm_undef 1EE FE01 FE01 pwm_undef pwm_undef 1EF FE01 FE01 pwm_undef pwm_undef 1F0 581E 581E FORCE_INTERRUPT FORCE_INTERRUPT 1F1 EE1A 201C INIT_RECEIVER_UART INIT_TRANSMIT_UART 1F2 2821 282B SERV_START_BIT_UART SERV_DATA_BITS_UART 1F3 2821 282B SERV_START_BIT_UART SERV_DATA_BITS_UART 1F4 EE01 EE01 UART_UNDEF UART_UNDEF 1F5 EE01 EE01 UART_UNDEF UART_UNDEF 1F6 EE01 EE01 UART_UNDEF UART_UNDEF 1F7 EE01 EE01 UART_UNDEF UART_UNDEF 1F8 2814 2812 immed_l immed_h 1F9 0002 FE00 Init_pwm pwm_undef 1FA 9019 FE16 Normal_H_L Normal_0 1FB 3006 3006 Normal_L_H Normal_L_H 1FC FE01 FE01 pwm_undef pwm_undef 1FD FE01 FE01 pwm_undef pwm_undef 1FE FE01 FE01 pwm_undef pwm_undef 1FF FE01 FE01 pwm_undef pwm_undef